Recent developments in fast semiconductor memories will lead to high-speed signal transmission rates of, for example, up to 7 Gbit/s. These high signal transmission rates require careful design considerations with respect to the implementation of an appropriate topology and a suitable design of interface circuits between the exterior of the chip and the chips internal circuitry.
Future generations of memory systems will likely arrange the memory chips in a chain which aims to increase the attainable storage density. For this chaining of the memory chips, serial high-speed interface circuits are required to include a repeater/re-driver function for data signals as well as command and address signals.
One advantageous topology of arranging the memory chips in such a chain is a shared loop forward architecture in which the write data signals and command and address signals and the read data signals to/from the memory chips share a common read/write bus, wherein the read and write data signals and command and address signals are propagated on a memory module in one and the same direction (unidirectional) through a shared loop forward bus.
FIG. 1 schematically shows an arrangement of four memory chips M1, M2, M3, M4, arranged and connected in the shared loop forward architecture on a memory module MMOD and to a memory controller C, each memory chip M1 to M4 having a dedicated rank Rank 1 to Rank 4 (or chip number) in a memory system. In the example of FIG. 1, a serial stream of write data signals and command and address signals WR/eCA is driven through the common shared loop forward bus from the memory controller C (not shown) to the first memory chip M1 on the memory module MMOD. Write data signals and command and address signals may be destined for the first memory chip M1 or for another one of the memory chips M2-M4 on the memory module MMOD. Therefore each memory chip M1-M4 has a repeater (or re-drive) function RE. This repeater or re-drive function is also required for re-driving read data through one or more memory chip on the memory module MMOD to the memory controller C. FIG. 1 further shows that each memory chip M1 to M4 on the memory module MMOD receives and drives a clock signal CLK and a separate rank select signal RS generated by the memory controller C and is supplied from the memory controller C separately, i.e., not within the write data/command and address signal stream WR/eCA. As shown, the clock signal CLK may be driven from the last memory chip M4 in the chain to the memory controller C (or optionally to another same memory module).
To implement certain interface processes and the re-drive function RE, each memory chip M1-M4 includes a high-speed interface circuit I. Each memory chip M1-M4 further includes a memory core MCORE and a memory core interface MCOREINT associated to the memory core MCORE.
FIG. 2 schematically shows an alternative example of an arrangement of four memory chips M1-M4 on a memory module MMOD in a chain having a shared loop forward architecture, wherein the arrangement of FIG. 2 differs from that of FIG. 1 only in that the rank select signal RS is not separately transferred from the memory controller C but included in the signal stream WR/eCA transmitted from the memory controller C. That is, the function of whether the high-speed interface circuit I of each memory chip M1-M4 exhibits the re-driver/repeater function RE or if the write data/command and address signals WR/eCA are alternatively to be processed within the memory chip is controlled by the rank signal RS included in the data/command and address signal stream.
Notably, in case the where data transfer between the memory controller C and the memory module MMOD and between the memory chips M1-M4 on the memory module MMOD is ruled by a protocol, and the data and command signals are organized in signal frames in accordance with the protocol, the memory core interface MCOREINT of each memory chip M1-M4 is required to include certain alignment procedures, a demultiplexing function, and a frame decoding function. The present invention, however, focuses on the functions and circuit construction of the high-speed interface circuit I rather than the functions and the circuit construction of the memory core interface MCOREINT.
For a system design of a memory module MMOD as it is shown in FIGS. 1 and 2, there are following objectives: same propagation direction on the memory module; same propagation delay for each memory chip (rank); same latency for each memory chip (rank); no functional cause of collision of write data signals or command and address signals as well as read data on the shared bus; and the timing calibration at the memory controller C should be simple.